Integrated circuits or electronic chips are ubiquitous, being contained in many electronic devices used by a person during a typical day, such as in cellular telephones, personal computers, automobiles, and even common household appliances like toasters. A chip includes a semiconductor die, which is made of semiconductor material such as silicon, and in which desired electronic circuitry is formed. For example, a memory chip is a chip containing a die in which electronic circuitry is formed for storing and retrieving data. A chip also includes a package that houses the die and includes pins that provide for electrical interconnection of the chip to external electronic components. Various different types of packages are utilized for chips, with the specific type of package being determined by numerous factors such as required heat dissipation, the physical size of the chip, and the number of interconnections needed from the die to external electronic components. Common packages for chips include dual in-line packages (DIPs), plastic leaded chip carriers (PLCC), Thin Small Outline Packages (TSOPs), pin-grid arrays (PGAs), ball-grid arrays (BGAs), and quad flat packs (QFPs).
In some situations, more than one die is housed in a given package to form what is commonly referred to as a “system in a package” (SIP) device or simply a SIP. The two or more die in this situation must be electrically interconnected, and depending on the type of package this interconnection may present difficulties. Specifically, difficulties arise when using any type of package including a lead frame, such as the DIP, PLCC, TSOP, and QFP packages previously mentioned. For example, a quad-flat pack (QFP) is a package having pins or external leads that project from all four sides of the package. QFP packages are relatively cheap and also are relatively thin (i.e., have a small height) compared to other types of packages, and accordingly may be utilized where cost and height of the package are of concern. A QFP package includes a lead frame and the physical structure of the lead frame and overall QFP package makes the interconnection of multiple dies in such a package problematic.
FIG. 1 is a simplified top view of a portion of a chip including a conventional QFP package containing a lead frame 100. The lead frame 100 includes a die paddle 102 on which two die 104 and 106 are mounted, with the die 104 being a dynamic random access memory (DRAM) and the die 106 being a memory controller in the example of FIG. 1. The die paddle 102 is supported by four support arms 108 (commonly called tie bars) attached to respective corners of the die paddle. Arranged around the periphery of the die paddle 102 are a number of bond fingers 110, several of which are shown along the top, bottom, left, and right edges of the paddle. These bond fingers 110 typically extend from all four sides of the QFP package to form the external leads of the QFP and are also coupled or connected through respective bonding wires 112 to corresponding bond pads 114 on one of the dies 104 and 106. The die paddle 102, bond fingers 110, bonding wires 112, and bond pads 114 are all formed from electrically conductive material, such as a metal, as will be appreciated by those skilled in the art. To simplify FIG. 1, some of the bond pads 114 on the dies 104 and 106 are not labeled with the reference indicator 114, although all the small squares contained on each of these dies correspond to respective bond pads. The illustrated bond pads 114 on each of the dies 104 and 106 merely serve to indicate that each die includes such bond pads and the number and arrangement of such bond pads may of course vary for different types of dies.
Each bond finger 110 and corresponding external lead function to route a respective electrical signal via a corresponding bonding wire 112 to or from the memory controller die 106. In general, bond fingers 110 may route respective electrical signals to both dies 104 and 106, although in the example of FIG. 1 such signals need only be routed to the memory controller die 106 since this die functions as the interface to the DRAM die 104. These signals would include address, data, and control signals in the example of FIG. 1, as will be appreciated by those skilled in the art.
The die paddle 102 is typically metal and is typically utilized as a ground plane, meaning that the paddle is coupled through bonding wires 112 to bond fingers 110 that receive ground signals, as shown for two bond fingers 110a and 110b along the right edge of the die paddle. Any bond pads 114 on the dies 104 and 106 that are to be coupled to ground are then simply “down bonded” to the die paddle 102, meaning such bond pads are coupled directly to the die paddle via a corresponding bonding wire 112. Several examples of down bonded ground wires 112a, 112b, and 112c are shown in FIG. 1. Note that in the present description when referring generally to a plurality of the same type of component, such as bonding wires, a number descriptor will be utilized and when referring to a specific one of the plurality of components a letter designation may be appended to the number to more precisely identify a specific one of the components.
There must also be electrical interconnection between the DRAM die 104 and memory controller die 106. In the example of FIG. 1, the memory controller die 106 requires control, address, and data signal interconnections to the DRAM die 104 to transfer data to and from the DRAM die. This interconnection of signals between the dies 104 and 106 is straightforward where the bond pads 114 are positioned along edges of the two dies that are adjacent one another. In FIG. 1 this corresponds to bond pads 114a positioned along the inner edge of the DRAM die 104 and bond pads 114b positioned along the adjacent inner edge of the memory controller die 106. The bonding wires 112 in this situation are simply routed as shown from each bond pad 114a on the DRAM die 104 to a corresponding bond pad 114b on the memory controller die 106.
In addition to the bond pads 114a and 114b along the adjacent inner edges of the two dies 104 and 106, there are also typically bond pads along other edges of at least one of the dies that also require interconnection to the other die. For example, in FIG. 1 the DRAM die 104 includes three bond pads 114c, 114d, and 114e positioned along an upper edge of the DRAM die and the memory controller die 106 includes three bond pads 114f, 114g, and 114h positioned along an upper edge of the memory controller die. The bond pad 114c on the DRAM die 104 may need to be electrically connected to the bond pad 114f on the memory controller die 106. Similarly, the bond pads 114d and 114e on the DRAM die 104 may need to be electrically interconnected to the bond pads 114g and 114h, respectively, on the memory controller die 106.
In this situation, bonding wires 112 cannot simply be utilized to interconnect the bonding pads 114c-e and 114f-h or else the bonding wires will short together or contact one another and thereby undesirably electrically interconnect multiple bond pads. This is illustrated in FIG. 1, where bonding wire 112d interconnects bond pads 114c and 114f, bonding wire 112e interconnects bond pads 114d and 114g, and bonding wire 112f interconnects bond pads 114e and 114h. These bonding wires 112d-f are likely to short-circuit or undesirably contact each other, as represented by the circle 116. Moreover, even if these bonding wires 112d-112f could initially be properly routed between the bond pads 114c-114e on die 104 and bond pads 114f-114g on die 106, subsequent manufacturing steps of the overall package or chip containing the lead frame may cause these bonding wires to short circuit. This could occur, for example, during encapsulation of the package during which an epoxy resin or other type of glue is formed over this entire structure.
The structure of a QFP package requires that bonding wires 112 be used to directly interconnect the required bond pads 114 on the two dies 104 and 106. This is in contrast to other types of packages such as ball grid arrays (BGAs) where there is an underlying substrate on which the two die 104 and 106 are mounted. This substrate functions like a miniature circuit board and simplifies the routing of the signals between the two die 104 and 106.
One approach to solving the problem of interconnecting bond pads 114 not located along the inner edges of the dies 104 and 106 is to alter the design of dies 104 and 106 so as to reposition the location of selected bond pads on the DRAM die 104 to be directly across corresponding bond pads on the memory controller die 106. Ideally, however, it is desirable that the same die 104 and 106 could be utilized whether the dies are being placed individually inside a QFP package, a ball grid array package, or any other type of package, of if they are placed inside a SIP chip. Repositioning the bond pads 114 on the dies 104 and 106 could make these die unsuitable for use individually in standard packages. Moreover, this redesign of dies 104 and 106 is relatively expensive and time consuming since it involves the cost of new mask layers used in the die fabrication process and the time it takes to fabricate new die.
Another approach for providing the required electrical interconnection of bond pads 114 not positioned along the inner edges of the dies 104 and 106 is to relocate these bond pads using a redistribution layer (“RDL”), which is a layer formed as an additive process on the top of each die. As its name implies, such a redistribution layer redistributes or repositions the locations of underlying bond pads 114 on the dies 104 and 106. With this approach, the bond pads 114f-h along the upper edge of the memory controller die 106 would be repositioned along the inner edge of this die to allow for easy connection to an adjacent bond pad 114 on the DRAM die 104 through a respective bonding wire 112. The same is true for the bond pads 114c-e along the upper edge of the DRAM die 104, with these pads being repositioned along the inner edge of this die for easy connection to corresponding bond pads on the memory controller die 106. This approach requires the design and actual physical formation of the redistribution layers on the dies 104 and 106. While this method of relocating the bond pads 114 is less expensive and faster than modifying the dies themselves, it is still undesirable. The inner edges of the dies 104 and 106 may already be fully populated with bond pads 114 thus be unable to accept new pads. This solution also requires an RDL be used on both dies 104 and 106.
Yet another approach is an interposer layer positioned under the dies 104 and 106. The interposer layer functions similar to the substrate previously described for a ball grid array to route connections for bond pads on the two dies 104 and 106, such as the bond pads 114c-e and 114f-h. Once again, this approach is relatively expensive and therefore undesirable, and also increases the vertical height of the QFP package and thereby contravenes one major advantage of a QFP package, namely the small overall height of the package. The same is true for the approach of stacking the two die 104 and 106, which also may not be practical if the size of the two die are incompatible.
There is a need in QFP or other lead frame packages that include more than one die of reliably and inexpensively electrically interconnecting the two die.